1. Field of the Invention
The present invention relates to an adaptive dead-time controller and, more particularly, to an adaptive dead-time controller for improving the conversion efficiency of a power converter in light load or no load conditions.
2. Description of the Related Art
As shown in FIG. 1, in a power supply circuit 2, a power converter 8 is used for receiving an external input voltage Vin and providing an output voltage Vo to a load device 6. A feedback control circuit 10 outputs a proper gate pulse to the power converter 8 according to the output voltage Vo and a current sense (CS) level for providing more or less power to a load device 6. For example, when a load device 6 presents a heavy load, the feedback control circuit 10 requires the power converter 8 to provide a higher output power to satisfy the power consumption of a load device 6; when a load device 6 presents a light load, the feedback control circuit 10 requires the power converter 8 to provide lower output power to conserve power. The power converter 8 can be a buck converter, a boost converter, a flyback converter or a forward converter for different circuits, and the feedback control circuit 10 generally utilizes a pulse width modulation (PWM) method to generate the gate pulse. The feedback control circuit 10 in FIG. 1 is a current mode control unit, which outputs the gate pulse according to the output voltage Vo and a switch current CS of a switch unit (not shown). Alternatively, the feedback control circuit 10 also can be a voltage mode control unit which only detects the output voltage Vo. A user can decide which kind of unit is most appropriate. Accordingly, how the feedback control circuit 10 dynamically adjusts the operation mode of the power converter 8 according to the loading conditions presented by a load device 6 is a very important factor for the output efficiency of the power supply 2.
Please refer to FIG. 2 and FIG. 3. FIG. 2 is a functional block drawing of the prior art feedback control circuit 10 and FIG. 3 is an operation timing of the circuit 10. The prior art feedback control circuit 10 comprises a control circuit, a feedback compensation circuit 17 and an input compensation circuit 18. The control circuit further comprises an error amplifier 11, a reference voltage generator 12, a comparator 13, an oscillator 14, an SR type flip-flop 15, and a gate driver 16.
The basic operation of the prior art feedback control circuit 10 is described as follows. The output voltage Vo is input into a negative end of the error amplifier 11 via the input compensation circuit 18. The error amplifier 11 compares the compensated output voltage with a reference voltage Vref generated by the reference voltage generator 12 and generates an error voltage Ve to the feedback compensation circuit 17 and a negative end of the comparator 13. The feedback compensation circuits 17 and the input compensation circuit 18 consist of resistors and capacitors, which are used for stabilizing the operations of the prior art feedback control circuit 10.
The comparator 13 compares the error voltage Ve with a voltage of a switch current CS output by a switch unit (not shown, but mounted in the power converter 8) to generate a reset signal Reset to the SR type flip-flop 15. An oscillation signal CLKOUT generated by the oscillator 14 regularly causes the gate pulse to return to a high voltage level.
When the voltage of the switch current CS output by the switch unit is smaller than the error voltage Ve, the reset signal Reset is kept at a low voltage level. The oscillation signal CLKOUT sets the gate pulse at high voltage level by setting the output of the SR type flip-flop 15 at a high voltage level. The voltage level of the gate pulse is not kept at a high level until the voltage of the switch current CS is larger than the error voltage Ve, and then the gate pulse is reset to a low voltage level. A pulse width of the gate pulse generated by a setting-resetting cycle determines the output power of the power converter 8.
Please refer to FIG. 4 and FIG. 5. FIG. 4 is a functional block drawing of the oscillator 14 and FIG. 5 is an operation timing of the oscillator 14. The oscillator 14 comprises a charging current source 140, a discharging current source 141, a switch capacitor 142, comparators 143 and 144, an SR type flip-flop 145, an inverter 146, and switch transistors 147 and 148. The comparator 143 and the comparator 144 compare the oscillation signal OSC with a high reference voltage VH and a low reference voltage VL respectively. If the oscillation signal OSC is higher than the high reference voltage VH, an output clock signal CLK2 of the comparator 143 switches to the high voltage level, and then an output clock signal CLK3 of the SR type flip-flop 145 is switched to the low voltage level, so the switch transistor 148 is active to reduce the voltage level of the oscillation signal OSC (discharged by the discharging current source 141). If the oscillation signal OSC is lower than the low reference voltage VL, the oscillation signal CLKOUT of the comparator 144 is at the high voltage level, and the output clock signal CLK3 is switched to a high voltage level, so that the switch transistor 147 is enabled to raise the voltage level of the oscillation signal OSC (charged by the charging current source 140). Accordingly, the oscillator 14 outputs the oscillation signal CLKOUT with a regular cycle.
However, the frequency of the oscillation signal CLKOUT is fixed, and the frequency of the gate pulse of the power converter 8 is also fixed. Gate pulses with a fixed frequency cause the power converter 8 to have high switching losses during light load or no load conditions.
Therefore, it is desirable to provide an adaptive dead-time controller to mitigate and/or obviate the aforementioned problems.